This invention relates to a semiconductor memory device, and more particularly to a redundant circuit for relieving defects in the memory cells arranged, for example, in the direction of row (or in the direction of word line).
Redundancy techniques have been applied to semiconductor memory devices to improve the yield and increase the proceeds from manufacture efficiently. Redundancy techniques are the techniques for replacing defective cells because of defects with spare cells previously provided.
FIG. 30 is a block diagram showing the main part of a semiconductor memory device with a conventional redundant circuit, such as a dynamic random access memory (DRAM).
In FIG. 30, a semiconductor memory device 10 comprises a memory cell array 11 and a spare cell array 12 for relieving defective memory cells in the memory cell array 11. The memory cell array 11 includes word lines WL and bit lines BL and has memory cells MC at the intersections of the individual word lines and bit lines BL. The spare cell array 12 includes spare word lines SWL and the bit lines BL and has spare memory cells (not shown) at the intersections of the spare word lines SWL and bit lines BL.
A row address buffer 13 receives address signals A0 to An supplied from the external device according to a row address strobe signal RAS and generates a row address signal. A column address buffer 14 receives an address signal supplied from the external device according to a column address strobe signal CAS and generates a column address signal. The row address signal outputted from the row address buffer 13 is supplied to a row decoder 15. The row decoder 15 selects a word line WL in the memory cell array 11 in accordance with the row address signal. The column address signal outputted from the column address buffer 14 is supplied to a column decoder 16. The column decoder 16 selects a bit line in the memory cell array 11 in accordance with the column address signal. An input/output buffer 17 holds write data and read data. Between the column decoder 16 and memory cell array 11, an I/O (input/output) gate 18 is provided. According to the output signal from the column decoder 16, the I/O gate 18 connects the bit line BL with the input/output buffer 17.
Near the spare cell array 12, there is provided a spare row decoder (SRD) 19 for selecting a spare word line SWL. A redundant memory circuit 20 stores the row addresses of defective memory cells. Between the redundant memory circuit 20 and row address buffer 13, a judgment circuit 21 is provided. The judgment circuit 21 compares the row address supplied from the row address buffer 13 with the row address of the defective memory cell stored in the redundant memory circuit 20. The judgment circuit 21, when these row addresses coincide with each other, deactivates the row decoder 15 and activates the spare row decoder 19.
The redundant memory circuit 20 is composed of, for example, fuses and latch circuits. When the result of the initial test (die sort test) has shown that there is a defective memory cell in the memory cell array 11, a specific fuse is blown by, for example, a laser and information on the defective row address corresponding to the defective memory cell is stored in a latch circuit.
The operation carried out up to the step of activating a word line will be explained.
The row address buffer 13 receives an external address signal according to the row address strobe signal RAS and generates a row address signal. Next, the judgment circuit 21 compares the row address signal with the defective row address stored in the redundant memory circuit 20. When the result of the comparison has shown that they coincide with each other, the output of the judgment circuit 21 deactivates the row decoder 15 and activates the spare row decoder 19, thereby selecting a spare word line SWL. When the result has shown that they do not coincide with each other, the output of the judgment circuit 21 deactivates the spare row decoder 19 and activates the row decoder 15. The row decoder 15 then selects a word line WL.
In the conventional method, each time the row address buffer 13 outputs a row address signal, the judgment circuit 21 compares the row address signal with the defective address signal. According to the result of the comparison at the judgment circuit 21, the row decoder 15 or spare row decoder 19 is activated or deactivated, thereby selecting a word line or spare word line. As a result, the comparison time at the judgment circuit 21 hinders the memory from being accessed at higher speed.